Synplicity and Forte Design Systems Deliver Industry's First Complete Design and Verification Path From C++ To PLDs
Companies Collaborate with Altera to Optimize C++ Flow for SOPC Designs
SUNNYVALE and SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 19, 2001--
Synplicity, Inc. (Nasdaq:SYNP - news), a leading supplier of software for
the design and verification of semiconductors, and Forte Design
Systems, Inc. today announced the availability of the industry's first
complete design and verification path from C++ to programmable logic
implementation. As a result of the companies' joint development
efforts, designers can use Forte's Cynthesizer C++-to-HDL product and
verification suite with Synplicity's Synplify Pro® RTL synthesis
solution to synthesize C++ code into a gate-level netlist for a broad
range of programmable logic devices (PLDs) from leading vendors,
including the Excalibur(TM) embedded processor solutions now available
from Altera Corporation (Nasdaq:ALTR - news).
Also today, Altera announced it will collaborate with Synplicity
and Forte to optimize this flow and endorse Cynlib C++ as an
alternative design language for system-on-a-programmable-chip (SOPC)
designs. Using this integrated solution for design and verification at
a higher level of abstraction, PLD designers can take advantage of the
high-performance flow as well as improved verification productivity
through use of sophisticated C++ testbenches and fast, unlicensed
simulation. A direct design path from C++ to PLDs enables designers to
meet stringent time-to-market requirements while improving
productivity and lowering design risk and costs.
"Traditionally, system architects and hardware designers have been
working in different languages at different levels of abstraction,
making it impossible to reuse valuable design and verification
knowledge," said Brett Cline, vice president of marketing at Forte
Design Systems. "As PLDs have become more complex, this has become a
serious design bottleneck. Using Forte's GigaScale design and
verification products, including Cynthesizer with the Synplify Pro
software, design teams now have a unified flow from high-level
architecture models through to gates with a consistent testbench
environment throughout the process. We are excited to work with
Synplicity to significantly reduce overall design and verification
times with this unique flow."
Joe Gianelli, director of business development and strategic
alliances at Synplicity, said, "We have worked closely with Forte to
enable smooth interoperability between our products because we believe
C++ offers many benefits for programmable logic designers. We also
believe the integration between our Synplify Pro software and Forte's
popular Cynlib C++-based solutions provides the industry's first
complete design and verification path from C++ to programmable silicon
and can help hardware designers maintain high-performance solutions
while accelerating the design of electronic systems from concept to
implementation."
Tim Southgate, vice president of software and tools marketing at
Altera, added, "One of the primary benefits of a
system-on-a-programmable-chip (SOPC) solution is the ability to
implement sections of a design as either software or hardware,
depending upon system performance objectives. Altera is committed to
working with Synplicity and Forte Design to provide a robust C++ to
PLD design flow that makes this powerful flexibility available to our
customers. Altera's Excalibur embedded processor solutions are here
today to take advantage of these exciting new capabilities."
The collaboration between Synplicity and Forte provides a smooth
and reliable flow that allows an engineer to enter a design specified
in Cynlib C++, Forte's open source C++ class library, directly into
Synplicity's Synplify Pro software to obtain a gate-level netlist. The
Synplify Pro software automatically interfaces with the Cynthesizer
software to transform the C++ code into intermediate hardware
description language (HDL) code and then a highly optimized gate-level
netlist for the target PLD.
C++ Benefits for PLD Designers
Programmable logic designers specifying designs in C and C++ can
achieve many productivity and performance benefits including:
- The rapid development of executable specifications that are
useful for early architectural exploration, including
unlicensed high-level simulation. Simulation of these models
allows the designers to make hardware/software tradeoffs
before an implementation is chosen.
- A high-performance, highly scalable, unified platform for the
integration of multiple design engineering teams including
system, software, firmware, verification and hardware groups.
The hierarchical methodology of C++ enables the entire system
to be modeled and simulated at speeds much greater than
traditional RTL simulation speeds.
- The quick implementation of complex algorithms, such as
graphics, routing or DSPs, significantly reducing design and
verification time.
Pricing and Availability
Synplicity's Synplify Pro synthesis software with an optimized
interface to Forte's Cynthesizer software is now available. Pricing
for the Synplify Pro software starts at $19,000 (U.S.). Current
customers on maintenance will be upgraded at no additional cost.
Forte's GigaScale design and verification products are now available.
Pricing for GigaScale products starts at $40,800. Cynlib is available
for free under an open source license at http://www.ForteDS.com.
About Forte's GigaScale Products and Cynthesizer
Forte's GigaScale design and verification products provide a
unique, high-performance, scalable flow from high-level C++ to RTL
HDL. By modeling in C++, design teams are able to verify designs
earlier in the process where simulation speeds are much faster than
with traditional HDL simulators and tradeoffs can still be made. Using
Forte's Cynthesizer product, C++ can automatically be converted to RTL
in a fraction of the time needed for hand implementation with the high
quality that is expected by RTL designers.
About the Synplify Pro Software
Synplicity's Synplify Pro software offers high quality of results
and fast runtimes with a feature set optimized to increase performance
and productivity for today's complex programmable devices. The
software takes designs written in VHDL or Verilog as input, and
compiles, optimizes and maps them into small, high-performance
netlists for all leading CPLD and FPGA devices.
About Altera
Altera Corporation, The Programmable Solutions Company®, was
founded in 1983 and is a leading supplier of programmable logic
devices (PLDs). Altera's CMOS-based PLDs are user-programmable
semiconductor chips that enhance flexibility and reduce time-to-market
for companies in the communications, computer peripheral, and
industrial markets. By using high performance devices, software
development tools, and sophisticated intellectual property cores,
system-on-a-programmable-chip (SOPC) solutions can be created with
embedded processors, memory, and other complex logic together on a
single PLD. Altera common stock is traded on The Nasdaq Stock Market
under the symbol ALTR. More information on Altera is available on the
Internet at http://www.altera.com.
About Forte Design Systems, Inc.
Forte Design Systems combines verification expertise with design
ingenuity to produce leading edge, high-quality products poised to
move the entire design and verification process to a higher level. The
company was formed by the recent merger of CynApps®, Inc. of San
Jose, California and Chronology® Corporation of Redmond, Washington.
Forte's headquarters are located at 1798 Technology Drive, in San
Jose, California, 95110, U.S.A. To find out more about this exciting
new company and the expansive array of products produced by Forte,
please visit us at www.ForteDS.com or call 800-800-6494.
About Synplicity
Synplicity, Inc. (Nasdaq:SYNP - news) is a leading provider of software
products that enable the rapid and effective design and verification
of semiconductors used in next-generation communications, computer,
consumer and military/aerospace electronics systems. The company
leverages its innovative logic synthesis, physical synthesis and
verification software solutions to improve performance and shorten
development time for complex programmable logic devices, application
specific integrated circuits (ASICs) and system-on-chip (SoC)
integrated circuits. Recognizing the company's industry-leading
position, Dataquest named Synplicity as the No. 1 provider of PLD
synthesis tools in 2000 with 45 percent market share. Synplicity's
fast, easy-to-use products offer high quality of results, support
industry-standard design languages (VHDL and Verilog) and run on
popular platforms. As of September 30, 2001, Synplicity employed 265
people in its 16 facilities worldwide. Synplicity is headquartered in
Sunnyvale, Calif. For more information on Synplicity, visit:
http://www.synplicity.com.
The specific features and functionality of new capabilities of
existing products and joint development efforts with third-parties as
described in this press release remain at the sole discretion of
Synplicity, Inc. and no warranty is made as to whether specific
functionalities of such new capabilities, interfaces with third-party
software or the success of joint development efforts with
third-parties will occur as described in the press release.
Synplicity and Synplify Pro are registered trademarks of
Synplicity, Inc. GigaScale Design and Verification, Cynlib and,
Cynthesizer are trademarks of Forte Design Systems, Inc. Altera, The
Programmable Solutions Company and Excalibur are trademarks of Altera
Corporation. All other brands or products are the trademarks or
registered trademarks of their respective owners.
Contact:
Altera Corporation
Bruce Fienberg, 408/544-6866
bfienber@altera.com
or
Forte Design Systems
Pamela Berndt, 425/869-4227 x112
pberndt@ForteDS.com
or
Tsantes & Associates/Porter Novelli (for Synplicity)
Steve Gabriel, 408/369-1500 x27
steve@tsantes.com
